1. Field of the Invention
The present invention relates to a driver circuit for a matrix-type display device and, more particularly, to a data electrode driver circuit that allows a gradation display according to current values by a display device that comprises a light emitting element for each pixel to gradation display and to a drive method.
2. Description of the Related Art
Liquid-crystal display devices and so forth are being implemented in accordance with the development of display device technology in recent years. An organic EL display device possesses characteristics such as a thinner shape and wider viewing angle than liquid crystal display devices.
Organic EL display devices include passive-matrix-type display devices and active-matrix-type display devices in which a TFT (Thin Film Transistor) is employed in a pixel circuit. Active-matrix-type display devices can be further classified into voltage-drive-type display devices and current-drive-type display devices on the basis of the drive method.
FIG. 2 shows a simplified view of a matrix-type display device.
Respective pixel circuits 6 are arranged at the points of intersection between a plurality of control electrodes 5, which are provided at predetermined intervals in the row direction, and a plurality of data electrodes 4, which are provided at predetermined intervals in the column direction. The pixel circuits employ about four or five TFTs to reduce variations in the current of the pixel circuits, whereby the image quality is enhanced. Further, although not illustrated, the display device also comprises a power supply for a data electrode driver circuit and a power supply for a control electrode driver circuit, and a control circuit for controlling the data electrode driver circuit and so forth. FIG. 27 shows a data electrode driver circuit that drives conventional data electrodes and pixel circuits.
Serially inputted digital image signals D00 to Dxx are held by a data conversion circuit 82 for the duration of a clock signal cycle in sync with a clock signal CLK. A data inversion signal INV is used in cases where half or more of the data of D00 to Dxx is to be inverted in comparison with previous data, and reduces the current consumed by the digital image signal wiring (data bus).
For example, if the previous data is 000011 and the next data is 111111, four of the six image signals are inverted. In this case, the data inversion signal INV is rendered 1 by the side from which data are outputted (CPU and so forth) and the inputted image signal is thus inverted from 111111 to 000000 and then inputted to the data conversion circuit. When signals inputted from the CPU side to the driver circuit side are inputted such that the image signal is 000000 and the INV is 1, the desired signal 111111 can be obtained as a result of inverting the image signal from 000000 to 111111 by a data conversion circuit 82.
If the previous data is 111111 and the present data is 110011, only two of the six image signals are inverted. In this case, data inversion is not executed by the side inputting the data (CPU and so forth). When the signals inputted from the CPU side are inputted such that the signal INV is 0 and the image signal is 110011, the desired signal 110011 is obtained without inversion being performed by the data conversion circuit 82.
A shift register 81 generates sampling signals SP sequentially in sync with the clock signal CLK. When a start signal STH is inputted, the shift register 81 generates sampling signals SP from the outputs of flip-flop circuits (abbreviated to ‘FF circuits’ hereinafter) as shown in FIG. 28. That is, the shift register 81 generates a sampling signal SP1 from the output of an FF circuit 81a, generates a sampling signal SP2 from the output of an FF circuit 81b, generates a sampling signal SP3 from the output of an FF circuit 81c, and generates a sampling signal SP4 from the output of an FF circuit 81d, and then sequentially holds digital image signals in a data register circuit 12 in sync with the sampling signals SP1, SP2, SP3, and then SP4.
When the capture of a predetermined number of image signals ends, the digital image signals held by the data register circuit 12 are all transferred to and stored in a data latch circuit 13 at the same time by means of a latch signal STB. A current driver circuit A 14 drives data electrodes 4 by outputting predetermined current values in accordance with the image signal.
FIG. 29 provides a detailed view of the current driver circuit A 14 and the data latch circuit 13.
Generally, because the voltage of a display-device drive unit is high in comparison with the voltage of a logic unit as far as the data latch circuit 13, a level shift circuit 13c for converting a low voltage to a high voltage is provided between the current driver circuit A 14 and a data latch 13a. 
If a image signal is an n-bit image signal, transistors (abbreviated to ‘Tr’ hereinbelow) 85a to 85f operate as n switches and perform control in accordance with the image signal. Tr 84a to 84f establish current values that are weighted with respect to a current value I of a reference current device 86 by means of n fixed current devices. For example, current drivers 14k with 64 levels, where n=6, are implemented. Current values in the order Tr 84a, 84b, 84c, 84d, 84e, and then 84f are then 1×I, 2×I, 4×I, 8×I, 16×I, and 32×I.
For example, if the image signal is 000000 and Tr 85a to Tr 85f are all OFF, a current does not flow to a load 87. Further, if the image signal is 111111 and Tr 85a to Tr 85f are all ON, a current of 63×I then flows to the load 87. In addition, the number of data electrodes 4, the number of control electrodes 5, and the number of current drivers 14k and so forth are optional depending on the number of pixels in the panel and the constitution of the pixel circuits. The load 87 is constituted by the data electrodes 4 and the pixel circuits 6.
When there is a current variation in the current drivers driving the pixel circuits, unevenness in the display (vertical line unevenness) then occurs. Generally, although a certain number of dot defects are permissible, not a single line defect can be permitted.
Therefore, in order to balance the variation in the characteristics of the A/D converter, D/A converter, amplifier, and so forth when an analog image signal is received, the provision of switching means on the input and output sides of the D/A converter, amplifier, and so forth to allow switching in optional cycles has been proposed (See Japanese Unexamined Patent Application Publication No. 09-152850 (first, second, and fifth drawings)).
However, the driving of this conventional display device several is confronted by several problems.
The first problem is that vertical line unevenness caused by variations in characteristics such as the current value of the current driver circuit is produced and there is a drop in the image quality.
The second problem is that, in the current drive method, the drive time is determined by the current value, load capacitance and drive voltage. Hence, when the number of pixels is high, the drive time is short and the load capacitance is large, meaning that a large current value is required and the electrical power consumption of the display device is then large.
For example, one horizontal period is 1/(frame frequency×number of scanning electrodes), and, hence, if the frame frequency is 60 Hz and the number of scanning electrodes is 320, one horizontal period is 1/(60×320)=approximately 52 μsec (because there is actually a vertical blanking period and a horizontal blanking period, one horizontal period is approximately 50 μsec).
In a voltage driving method for a liquid crystal display device or the like, data electrodes can be driven at a high speed of approximately 1.5 μsec by an amplifier with a high drive performance such as a voltage follower. Approximately 30 data electrodes can be written by one D/V converter (the conversion of a digital signal to a voltage-value analog value is abbreviated to ‘D/V conversion’ and the conversion of a digital signal to a current-value analog value is abbreviated to ‘D/I conversion’), and hence there may be 720/30=24 D/V converters.
In a current drive method for an organic EL display device, if driving takes place by means of a minute current of about 1 μA and the load capacitance is 10 pF, the time taken is t=CV/I=10 pF×5V/1 μA=50 μsec. That is, because time-division driving, which is generally performed by liquid-crystal display devices, is impossible, 720 D/I converters are required, which is the same number as the number of data electrodes.
Therefore, in the voltage drive method, driving can be performed at high speed by means of D/V converters, and therefore the write time is substantially constant irrespective of the image signal. However, in the current drive method, the write time is determined by the current value and load capacitance, and it is therefore difficult to drive a plurality of data electrodes using time division by means of a single D/I converter. Hence, the same number of D/I converters as data electrodes must be provided. Further, in the current drive method, if the number of pixels increases, the load capacitance increases and the drive time is shortened, meaning that there is the problem that the drive time is inadequate.
A third problem is that a conventional current driver circuit is unable to obtain current values that match the Gamma characteristic.
A fourth problem is that the circuit scale increases. In the technology in Japanese Unexamined Patent Application Publication No. 09-152850, an inputted signal is an analog signal, which is first A/D converted and then D/A converted and switching means are provided on the input and output sides of the D/A conversion to balance the variations in the characteristics of the D/A conversion circuit.
However, in small-scale display devices such as the latest cellular phones, the definition and number of gradations is increasing and the number of pixels is QVGA (240×RGB×320 pixels) or more. Advances in digital technology are leading to 6-bit or higher digital signals.
Therefore, when switching means are provided on the input side of the D/A conversion circuit, the number of switches connected to the input electrode of a single D/A converter is then (number of D/A converters×number of bit of digital image signal), and hence the number of the switches is huge. In this case, in the switching of image signals, the required number of switches on the input side of a single D/I converter is as many as 720×6=4,320, and, therefore, for the whole of the display device, as many as 720×3,110,400 switches are required.